The present invention relates to a semiconductor device and a method of manufacturing the same.
In general, semiconductor storage devices store information, such as data and program commands, and are generally classified into dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices. A DRAM device is a memory from which data stored therein can be read. Information can be read from and written into a DRAM device, but the information stored in a DRAM device disappears if the information is not periodically re-written into the DRAM device while power is on. As described above, a DRAM device must be continuously refreshed, but is widely used as a high-capacity memory device because it has a low price per memory cell and a high degree of integration.
A metal-oxide semiconductor field effect transistor (hereinafter referred to as an ‘MOSFET’), chiefly used in a memory device such as a DRAM device and logical elements, has a structure in which a gate oxide layer, a polysilicon layer, gate metal, and a gate hard mask layer are deposited over a semiconductor substrate and gates are then stacked to form a channel through mask and etch processes.
As the size of a semiconductor device is reduced, the length of a channel is also reduced. As the length of the channel of the semiconductor device is reduced, a short channel effect and a gate-induced drain leakage (GIDL) may occur. Thus, in order to improve the short channel effect and the GIDL characteristic, the length of a gate channel needs to be increased. However, if the gate channel length increases, gate resistance increases, and the GIDL characteristic becomes severe in a region where a gate region and a source/drain region overlap with each other.
FIG. 1 illustrates a cross-sectional view of a conventional semiconductor device.
Referring to FIG. 1, isolation regions (also referred to as “isolation structures”) 120 defining active regions 110 are formed in a semiconductor substrate 100 including a cell region 1000a and a peripheral region 1000b. 
An interlayer insulating layer 130 is formed over the active regions 110 and the isolation regions 120. After a photoresist layer (not shown) is formed on the interlayer insulating layer 130, photoresist patterns (not shown) are formed by performing exposure and development processes employing buried gates of the cell region 1000a as a mask. The interlayer insulating layer 130, the isolation regions 120, and the active regions 110 are etched by using the photoresist patterns as an etch mask, thereby forming buried gate regions 135 only in the cell region 1000a. 
A conductive layer is buried in the buried gate regions 135. Gate electrode patterns 140 are formed in the respective buried gate regions 135 by removing portions of the conductive layer in the buried gate regions 135. Next, a nitride layer 150 is formed over the buried gate regions 135 and the interlayer insulating layer 130.
If a process of forming gate patterns or other patterns is performed on the peripheral region 1000b after the buried gates are formed in the cell region 1000a as described above, an oxidation gas may be introduced through the isolation region 120 between the cell region 1000a and the peripheral region 1000b in an oxidation process of the gate patterns, as indicated by ‘A’. Accordingly, agate oxide intensity (GOI) characteristic of the cell region 1000a may be deteriorated because the gate electrode patterns 140 in the cell region 1000a may be oxidized by the oxidation gas introduced thereto.